Non-volatile memory cells having a floating gate for the storage of charges thereon are well known in the art. Referring to FIG. 1 there is shown a cross-sectional view of a non-volatile memory cell 10 of the prior art. The memory cell 10 comprises a single crystalline substrate 12, of a first conductivity type, such as P type. At or near a surface of the substrate 12 is a first region 14 of a second conductivity type, such as N type. Spaced apart from the first region 14 is a second region 16 also of the second conductivity type. Between the first region 14 and the second region 16 is a channel region 18. A word line 20, made of polysilicon is positioned over a first portion of the channel region 18. The word line 20 is spaced apart from the channel region 18 by an silicon (di)oxide layer 22. Immediately adjacent to and spaced apart from the word line 20 is a floating gate 24, which is also made of polysilicon, and is positioned over another portion of the channel region 18. The floating gate 24 is separated from the channel region 18 by another insulating layer 30, typically also of silicon (di)oxide. A coupling gate 26, also made of polysilicon is positioned over the floating gate 24 and is insulated therefrom by another insulating layer 32. On another side of the floating gate 24, and spaced apart therefrom, is an erase gate 28, also made of polysilicon. The erase gate 28 is positioned over the second region 16 and is insulated therefrom. The erase gate 28 is also immediately adjacent to but spaced apart from the coupling gate 26 and to another side of the coupling gate 26. In the operation of the memory cell 10, charges stored on the floating gate 24 (or the absence of charges on the floating gate 24) control the flow of current between the first region 14 and the second region 16. Where the floating gate 24 has charges thereon, the floating gate 24 is programmed. Where the floating gate 24 does not have charges thereon, the floating gate 24 is erased.
The memory cell 10 operates as follows. During the programming operation, when charges are stored on the floating gate 24, a first positive voltage is applied to the word line 20 causing the portion of the channel region 18 under the word line 20 to be conductive. A second positive voltage is applied to the coupling gate 26. A third positive voltage is applied to the second region 16. Current is applied to the first region 14. The electrons are attracted to the positive voltage at the second region 16. As they near the floating gate 24, they experience a sudden increase in the electric field caused by the voltage applied to the coupling gate 26, causing the charges to be injected onto the floating gate 24. Thus, programming occurs through the mechanism of hot electron injection. During the erase operation when charges are removed from the floating gate 24, a high positive voltage is applied to the erase gate 28. A negative voltage or ground voltage can be applied to the coupling gate 26 and/or the word line 20. Charges are transferred from the floating gate 24 to the erase gate 28 by tunneling through the insulating layer between the floating gate 24 and the erase gate 28. In particular, the floating gate 24 may be formed with a sharp tip facing the erase gate 28, thereby facilitating the Fowler-Nordheim tunneling of electrons from the tip on the floating gate 24 and through the insulating layer between the floating gate 24 and the erase gate 28 onto the erase gate 28. During the read operation, a first positive voltage is applied to the word line 20 to turn on the portion of the channel region 18 beneath the word line 20. A second positive voltage is applied to the coupling gate 26. A voltage differential is applied to the first region 14 and the second region 16. If the floating gate 24 were programmed, i.e. the floating gate 24 stores electrons, then the second positive voltage applied to the coupling gate 26 is not able to overcome the negative potential induced by electrons stored on the floating gate 24 and the portion of the channel region 18 beneath the floating gate 24 remains non-conductive. Thus, no current or a minimal amount of current would flow between the first region 14 and the second region 16. However, if the floating gate 24 were not programmed, i.e. the floating gate 24 is positively charged, then the second positive voltage applied to the coupling gate 26 is able to cause the portion of the channel region 18 beneath the floating gate 24 to be conductive. Thus, a current would flow between the first region 14 and the second region 16.
As is well known, memory cells 10 are typically formed in an array, having a plurality of rows and columns of memory cells 10, on a semiconductor wafer. After the devices are fabricated on a wafer, the devices on the wafer are subject to a test to determine the ability of each memory cell 10 to retain its programmed or erased state, in particular, the ability of the floating gate 24 in each memory cell 10 to retain its charge. During testing the memory cell 10 is first programmed, to place charges on the floating gate 24, or erased, to remove charges from the floating gate 24. The device is then subject to a high temperature bake. Finally, each memory cell 10 in the device is subject to a read operation in which the read current from the memory cell 10 under test is compared to the read reference current.
Referring to FIG. 2 there is shown a graph of the read current of various memory cells with their data. The cells with the erased state typically would have a higher read current 40 compared to the read current 42 from memory cells with zero charge on the floating gates, which typically have a higher current than the read current 44 from the programmed memory cells. Due to dispersion of parameters of cell integrated in a memory array, the read current 42 of some cells can be higher than the read reference current, and the read current 42 of some cells can be lower than the read reference current.
In the event the memory cell 10 has a leakage path for charge through dielectrics surrounding floating gate 24, the read current from such a defective memory cell 10 having an erased state, would decrease and tend to have the characteristics of current 42. This condition cannot be detected after a high temperature bake if the read current from the defective memory cell 10 under test remains above the read reference current. Similarly, the read current from a defective memory cell 10 having a programmed state, would increase and tend to have the characteristics of current 42. This condition cannot be detected after a high temperature bake if the read current from a defective memory cell 10 under test remains below the read reference current.
Due to these characteristics of the non-volatile memory cell 10, testing of a memory device with memory cells 10 of the prior art have involved two steps. In a first step, a first data pattern is stored in all memory devices followed by a first baking step, followed by a testing step to determine the read current of each memory cell 10 and compare them to the read reference current. In a second step a second data pattern, which is a mutually inverse pattern of the first data pattern, is stored in all memory devices followed by a second baking step, followed by a testing step to determine the read current of each memory cell 10 and compare them to the read reference current. Because the time to store the data pattern in all memory devices and the time to bake the devices is considerable, this has increased the cost of testing the memory device. Even with the two baking process of the prior art, however, some defective memory cells 10 may be undetected after the data retention screening tests. For example, a defective cell 10 has a read current 42 above the read reference current. In the first test, when the defective cell 10 is in the erased state, the read current from such a cell would decrease and tend to have the characteristics of current 42, so that its read current remains above the read reference current, and the defective cell 10 would not be detected. In the second test, when the defective cell 10 is in the programmed state, the read current from such a cell would increase and tend to have the characteristics of the read current 42. However, if leakage is too slow during the bake process, the read current from the defective cell 10 would not have time to increase above the read reference current during the baking process. Therefore, because the read reference current is typically close to the read current 42, leakage during baking process is typically slow and some defective cells 10 may remain undetected after data retention screening.